Programmability in the network has accelerated in-network applications like NATs, firewalls, caching, etc. However, much of this programmability is only compile-time. Outside changing a few configuration parameters or packet processing rules, changing the functionality requires taking the network element offline and reflashing it. We explore the use of FPGA partial reconfiguration primitives to reprogram network elements piece by piece without requiring to take the whole device offline. We identify key requirements such a solution must provide and find that existing work on enabling runtime reconfiguration does not fully meet these requirements. We explore potential ways to meet all the key requirements. We build and test a preliminary prototype on Alveo U280 FPGA board to validate the feasibility of using FPGA partial reconfiguration to provide runtime reconfiguration.

This report documents our preliminary study into the implementation of a runtime reconfigurable packet processing pipeline on an FPGA NIC. We hope this report provides useful guidance in designing similar artifacts or using our code (https://github.com/StaRR-NIC/starrnic-public, https://github.com/StaRR-NIC/xup_vitis_network_example/blob/starrnic/Notebooks/measure_exp.py).

*The University of Texas at Austin

18 pages

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