CMU-CS-18-122
Computer Science Department
School of Computer Science, Carnegie Mellon University



CMU-CS-18-122

Formal Verification of Pipilined Y86-64
Microprocessors with UCLID5

Randal E. Bryant

October 2018

CMU-CS-18-122.pdf


Keywords: Formal verification, Microprocessor verification, UCLID5

This work reports on the verification of a complex instruction set computer (CISC) processor,named Y86-64, styled after the Intel64 instruction set using the UCLID5 verifier. We developed a methodology in which the control logic is translated into UCLID5 format automatically, and the pipelined processor and the sequential reference version were described with as much modularity as possible. This work provides confidence in the processor designs presented in the Bryant-O'Hallaron textbook on computer systems, and it alsO Provides a case study for the capabilities and performance of UCLID5.

41 pages



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