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CMU-CS-05-101
Computer Science Department
School of Computer Science, Carnegie Mellon University
CMU-CS-05-101
Adding Faster with Application Specific Early Termination
David Koes, Tiberiu Chelcea, Charles Onyeama, Seth Copen Goldstein
January 2005
CMU-CS-05-101.ps
CMU-CS-05-101.pdf
Keywords: asynchronous hardware, arithmetic and logic structures,
high-speed arithmetic, applicationspecific optimization
This paper presents a methodology for improving the speed of
high-speed adders. As a starting point, a previously proposed
method, called speculative completion, is used in which
fast-terminating additions are automatically detected. Unlike
the previous design, the method proposed in this paper is able
to adapt dynamically to (1) application-specific behavior and
(2) to adder-specific behavior, resulting in a higher detection
rate of fast additions and, consequently, a faster average-case
speed for addition. Our experimental results show detection rates
of over 99%, and adder average-case speed improvements of up to 14.8%.
20 pages
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