The lithographically-produced CMOS transistor has been the key technology that has enabled the information revolution. However, in the near future the limitations, both technical and economic, introduced by lithographic fabrication may inhibit further decreases in feature size. Chemically assembled electronic nanotechnology (CAEN) is a promising alternative to CMOS for constructing circuits with device sizes in the tens of nanometers, far smaller than is thought possible using lithography. In this paper we examine and contrast the constraints imposed by lithographic versus CAEN fabrication; the key limitation is that three-terminal devices, such as transistors, will be impractical at the nanoscale. We demonstrate that these constraints can be satisfied by outlining an architecture that uses only two-terminal CAEN devices to compute without transistors. One crucial requirement of this design circuit is that it be able to restore signals to a reference state without transistors. We present preliminary results for a molecular latch, constructed from molecular resonant tunneling diodes (RTDs) that can perform signal restoration, I/O isolation, and voltage buffering without transistors at the nanoscale.

19 pages

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