Computer Science Department
School of Computer Science, Carnegie Mellon University


Program Slicing of Hardware Description

E.M. Clarke, M. Fujita*, S.P. Rajan*, T. Reps**
S. Shankar, T. Teitelbaum***

March 1999

Keywords: Hardware description languages, program slicing, VHDL, software engineering, model checking, formal verification

Hardware description languages (HDLs) are used today to describe circuits at all levels. In large HDL programs, there is a need for source code reduction techniques to address a myriad of problems in design, simulation, testing, and formal verification. Program slicing is a static program analysis technique that allows an analyst to automatically extract portions of programs relevant to the aspects being analyzed. We extend program slicing to HDLs, thus allowing for automatic program reduction to let the user focus on relevant code portions. We have implemented a VHDL slicing tool composed of a general inter-procedural slicer and a front-end that captures VHDL execution semantics. This report provides an introduction to the theory of inter-procedural program slicing, a discussion of how to slice VHDL programs, a description of the resulting tool, and a discussion of some applications and experimental results.

22 pages

*Fujitsu Labs of America, Sunnyvale, CA
**University of Wisconsin, Madison, WI and Grammatech, Inc., Ithaca, NY
***Cornell Univerity, Ithaca, NY and Grammatech, Inc., Ithaca, NY

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