Thread-Level Data Speculation (TLDS) is a technique which enables the optimistic parallelization of applications despite uncertainty as to whether data dependences exist between the resulting threads which would normally make them unsafe to execute in parallel. The basic idea is to speculate that dependences do not exist, and to then recover and restart whenever dependences do occur dynamically. TLDS can accelerate performance when the gain from increased thread-level parallelism outweighs the overhead of failed speculation. The bulk of the support for TLDS is managed by software, but hardware provides two key pieces of functionality through an extension to invalidation-based cache coherence: (i) detecting dependence violations, and (ii) buffering speculative side-effects until they can be safely committed to memory. This paper explores a number of issues regarding architectural support for TLDS, including the software interface to our new hardware mechanisms (which includes extensions to the instruction set), the cache coherence protocol, and further details on how this scheme might be implemented within a modern memory hierarchy. We note that this document is a snapshot of our work in progress in this area, and we expect to refine our scheme in the future as we conduct further experiments as part of the STAMPede project.

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